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ISL6719
Data Sheet October 1, 2007 FN6555.1
100V Linear Bias Supply
The ISL6719 is a low cost linear regulator for generating a low voltage bias supply from intermediate distributed voltages commonly used in telecom and datacom applications. It provides a single adjustable output rated at 100mA from either the input source or an auxiliary source such as a transformer winding. The auxiliary source is selected whenever it has sufficient voltage to sustain the output. The ISL6719 may be used as a start-up or a continuous low power regulator. When operating as a start-up regulator, it is capable of sourcing 100mA from a 100V source for short durations. This period of time allows the power supply to start-up and provide an alternate power source, such as the output of a transformer winding, to the AUXIN input. This allows the regulated output to operate from a lower source voltage to minimize power loss.
Features
* 100+ Volt Input Capability * Adjustable Output from 1.5V to 20V * Up to 100mA Output Current * Overcurrent Protection * Over-Temperature Protection * ENABLE and ENABLE_N Inputs * Package Compliant with IPC2221A, Creepage and Clearance Spacing Requirements * Pb-Free (RoHS Compliant)
Applications
* Telecom/Datacom DC/DC Converters * Low Power Bias Supplies
Ordering Information
PART NUMBER (Note) ISL6719ARZ* PART TEMP. PACKAGE MARKING RANGE (C) (Pb-Free) 19AZ -40 to +105 9 Ld DFN PKG. DWG. # L9.3x3
Pinout
ISL6719 (9 LD DFN) TOP VIEW
VPWR
*Add "-T" suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
AUXIN VSW VSW_FB
1
9 GND 8 ENABLE_N
2 3 4
7 ENABLE 6 COMPB 5 COMPA
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
Functional Block Diagram
0V TO 40V VPWR 105V MAX INPUT SELECTOR 1.5V TO 20V @ 100mA VSW REGULATOR INT. BIAS ENABLE + BG + GND COMPA TMON +150C TRIP +95C CLEAR INT. BIAS COMPB VPWR OK TEMP OK VSW INT. BIAS + _ 1.5V REF VSW_FB AUXIN
+ -
2
START/STOP UV COMPARATOR POR + BG
FN6555.1 October 1, 2007
ISL6719
ENABLE INT-ENABLE
ENABLE_N
Typical Application
CONVERTER POWER STAGE
VIN +
+VOUT
17V TO 100V
3
FN6555.1 October 1, 2007
VIN-
RETURN
ENABLE DISABLE
ISL6719
1 VPWR
GND 9 FEEDBACK AMPLIFIER
ENABLE_N 8 2 AUXIN ENABLE 7 3 VSW COMPB 6 4 R1 ISL6719 COMPA 5 VSW_FB C3 220pF PWM
C1
C2 1.0F
R2
ISL6719
Absolute Maximum Ratings
Supply Voltage, VPWR . . . . . . . . . . . . . . . . . . GND - 0.3V to +105V AUXIN, VSW_FB . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +40V COMPB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +30V VSW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +25V All Others . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.0V
Thermal Information
Thermal Resistance (Typical, Notes 1, 2) JA (C/W) JC (C/W) 9 Ld DFN . . . . . . . . . . . . . . . . . . . . . . . 54 2.8 Maximum Junction Temperature . . . . . . . . . . . . . . .-55C to +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Temperature Range ISL6719AARZ . . . . . . . . . . . . . . . . . . . . . . . . . . .-40C to +105C Supply Voltage Range (Typical). . . . . . . . . . . . . . 18VDC to 80VDC
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 3. All voltages are with respect to GND.
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 2 and "Typical Application" on page 3. 17V < VPWR < 100V, CVSW = 1F, IVSW = -3mA, VSW Enabled, TA = -40C to +105C (Note 4), Typical values are at TA = +25C. TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER SUPPLY VOLTAGE (VPWR) Supply Voltage Start-Up Current (IVPWR) Operating Current (IVPWR) VPWR = 12V
100 250 1.1 1.1 1.1 450 2.0 2.0 2.0
V A mA mA mA
VSW Enabled, VPWR = 100V, VSW = 10V, 20V, IVPWR - IVSW VSW Disabled, VPWR = 100V, AUXIN Biased at 40V, VSW Enabled, VPWR = 100V, VSW = 10V, 20V, IVSW = -100mA
UVLO START Threshold UVLO STOP Threshold Hysteresis AUXILIARY VOLTAGE (AUXIN) Maximum Bias OUTPUT VOLTAGE (VSW) Load Capacitance Range Overall Accuracy Setpoint Range Reference
VSW Disabled VSW Disabled UVLO START - UVLO STOP
13.0 12.0 0.8 1.2
16.5 15.0 1.7
V V V
VPWR = 17V, 100V
40
V
Note 5 VPWR = 18V, 100V, VSW = 5V, 10V, 12V AUXIN = 15V, IVSW = -3mA to -100mA VPWR = 100V, AUXIN = 30V VSW_FB = VSW
0.47 -5 1.55 1.45
1.0
1.5 +5 20
F % V V
1.50
1.55
Source Voltage Headroom (AUXIN - VSW) VPWR = 17V, VSW = 10V, IAUXIN = 0.95*IVSW IVSW = -100mA IVSW = -50mA Source Voltage Headroom (VPWR - VSW) VSW = 20V, AUXIN = 0V IVSW = -100mA IVSW = -50mA Minimum Required Load 6.2 5.2 -3 V V mA 1.8 1.4 3.0 2.0 V V
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FN6555.1 October 1, 2007
ISL6719
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to "Functional Block Diagram" on page 2 and "Typical Application" on page 3. 17V < VPWR < 100V, CVSW = 1F, IVSW = -3mA, VSW Enabled, TA = -40C to +105C (Note 4), Typical values are at TA = +25C. (Continued) TEST CONDITIONS VSW_FB = 0V, VPWR = 100V, AUXIN = 40V TA = +125C, 1000 hours (Note 5), VPWR = 48V, VSW = 10V, IVSW = -10mA, AUXIN = 15V VPWR = 48V, AUXIN = 17V, VSW = 15V VPWR = 48V, AUXIN = 15V, VSW = 10V VPWR = 100V, AUXIN = 40V, VSW = 10V, VSW_FB = 1.5V Note 5 -100 -100 -0.5 170 220 0.7 VSW + 5.0 -230 -400 1.5 270 MIN 22 0.3 TYP MAX 25 UNITS V %
PARAMETER Maximum VOUT, Faulted VSW_FB Long Term Stability
Operational Current (source) Current Limit VSW_FB Bias Current COMPA, COMPB Recommended Capacitance COMPA Voltage COMPB Voltage ENABLE, ENABLE_N High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Hysteresis Pull-Up Resistance Turn-On Delay Turn-Off Delay THERMAL PROTECTION Thermal Shutdown Thermal Shutdown Clear Hysteresis NOTE:
mA mA A pF V V
VPWR = 48V, AUXIN = 0V VPWR = 48V, AUXIN = 0V VPWR = 48V, AUXIN = 0V VENABLE =VN_ENABL =0V TVSW,10% - TENABLE, TVSW,10% - TENABLE_N, IVSW = -3mA TVSW,10% - TENABLE, TVSW,10% - TENABLE_N, IVSW = -50mA
2.5 1.6 0.7 -
3.0 2.0 1.0 100 25 40
3.6 2.5 1.3 -
V V V k s s
150 95 55
C C C
4. Specifications at -40C and +105C are guaranteed by +25C test with margin limits. 5. Limits established by characterization and are not production tested.
Typical Performance Curves
5.5 5.0
VPWR - VSW (V) AUXIN - VSW (V)
2.5
4.5 4.0
2.0
1.5
3.5 3.0
0
20
40
60
80
100
1.0
0
20
40
60
80
100
VSW CURRENT (mA)
VSW CURRENT (mA)
FIGURE 1. VPWR - VSW vs IVSW @ AUXIN = 0V, +25C
FIGURE 2. AUXIN - VSW vs IVSW @ VPWR = 17V, +25C
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FN6555.1 October 1, 2007
ISL6719 Typical Performance Curves
1.002 VSW = 20V, AUXIN = 30V
NORMALIZED OUTPUT VOLTAGE
(Continued)
1.0010 VSW = 5V 1.0005 VSW = 10V 1.0000 VSW = 12V 0.9995
NORMALIZED REGULATION
1.001 VSW = 1.5V, AUXIN = 15V
VSW = 5V, AUXIN = 15V 1.000
0.999 VSW = 12V, AUXIN = 15V 0.998 VSW = 15V, AUXIN = 30V 0.997 -40 -25 -10 5 20 35 50 65 80 95 110
0.9990 0
10
20
30
40
50
60
70
80
90
100
TEMPERATURE (C)
LOAD (mA)
FIGURE 3. VSW REGULATION vs TEMPERATURE @ VPWR = 100V, IVSW = 3mA
FIGURE 4. VSW REGULATION vs LOAD @ VPWR = 18V, AUXIN = 15V, +25C
Pin Descriptions
VPWR
VPWR is the power connection for the IC. UVLO enables/disables the output and places the device into a standby mode even if AUXIN is externally biased. To optimize noise immunity, bypass VPWR to GND with a ceramic capacitor as close to the VPWR and GND pins as possible.
or low). The minimum output current capability is 100mA. VSW requires a minimum load of 3mA.
VSW_FB
The feedback pin for VSW. A divider from VSW to ground sets feedback for VSW and determines the output voltage.
COMPA, COMPB
A compensating capacitor is placed between COMPA and COMPB to stabilize the control loop. The values may vary depending on the output load and capacitance applied between VSW and GND, but for all applications having a 1.0F load capacitor, a 220pF compensation capacitor is recommended. The voltage at COMPA is nominally 0.7V. The voltage at COMPB is nominally VSW +5.0V.
AUXIN
This is the input for an external bias source typically provided by an auxiliary transformer winding. This input is not required and may be grounded or left open. Maximum input bias is 40V.
ENABLE
The positive logic on/off control input. A logic high enables VSW. Asserting this signal low turns off VSW. ENABLE and ENABLE_N are logically ORed. Either signal can enable VSW, but both must be false to disable VSW.
Functional Description
Features
The control circuitry used in Telecom/Datacom DC/DC converters typically requires an operating bias voltage significantly lower than the source voltage available to the converter. Many applications use a discrete linear regulator from the input source to create the bias supply. Often an auxiliary winding from the power transformer is used to supplement or replace the linear supply once the converter is operating. The auxiliary winding bias voltage may require regulation as well to minimize the voltage variation inherent in slave windings. When implemented discretely, this circuitry occupies significant PWB area, a considerable problem in today's high density converters. The ISL6719 linear regulator simplifies the start-up and operating bias circuitry needed in Telecom and Datacom DC/DC converters by integrating these functions, and more, in a small 3mm x 3mm DFN package.
ENABLE_N
The negative logic on/off control input. A logic low enables VSW. Asserting this signal high turns off VSW. ENABLE and ENABLE_N are logically ORed. Either signal can enable VSW, but both must be false to disable VSW.
GND
Signal and power ground connections for this device.
VSW
This is the switched regulated low voltage output supply that is derived from VPWR or AUXIN. Its output is adjustable from 1.5V to 20V using an appropriate divider from VSW to VSW_FB. Protection circuitry prevents the output from exceeding 25V in the event of a fault on VSW_FB (short high
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FN6555.1 October 1, 2007
ISL6719
AUXIN
AUXIN is the auxiliary input of the ISL6719, accepting bias voltage whenever the input source voltage, VPWR, is above its undervoltage lockout (UVLO) threshold. VSW selects AUXIN as its source when it is capable supporting the load on VSW. Otherwise VPWR is selected. AUXIN can accept voltages up to 40V maximum. Voltages in excess of 40V, including transients, will cause permanent damage to the device. Care should be taken when connecting external sources through very long traces or lead wires. The lead inductance may cause unexpected transients in excess of the device's ratings. In such circumstances it is recommended that a small resistor be placed between AUXIN and the external source to dampen the transient. A value of 10 to 100 is usually sufficient.
VSW 1 VPWR GND 9
ENABLE_N 8 2 3 4 R1 C2 1.0F ENABLE AUXIN 7
6 VSW COMPB COMPA 5 VSW_FB
R2
C3 220pF
VSW
VSW is the switched output and may be turned on and off using the ENABLE or ENABLE_N pins. VSW is adjustable from 1.5V to 20V, but must always be at least 6.2V lower than VPWR at rated load. Additionally, VSW must be at least 3.0V lower than AUXIN for it to function as the source for VSW. As the differential voltage between AUXIN and VSW drops below 3.0V, the input current will shift from AUXIN to VPWR. The voltage headroom required is load dependent. See Figures 1 and 2. VSW preferentially uses AUXIN as its input source, but if AUXIN is unable to supply adequate voltage, VPWR is selected as the alternate input source. VSW is capable of delivering up to 100mA continuously, depending on power dissipation and the thermal environment in which the device is placed. The output voltage is adjusted using the VSW_FB input. VSW is set with a resistor divider from VSW to ground with the central node connected to VSW_FB. Refer to Figure 5.
R1 + R2 VSW = V REF -------------------- - I BIAS R 1 R
2
FIGURE 5. VSW ADJUSTMENT AND COMPENSATION
TRACE 1: VSW
TRACE 2: IVSW
V
(EQ. 1)
Referring to Equation 1, VREF is nominally 1.5V and IBIAS has a maximum value of 1.5A. The error introduced by the VSW_FB bias current can be minimized by making the product of R1 x IBIAS small, relative to the magnitude of the desired output voltage. For example, setting R1 x IBIAS equal to 0.5% of VSW yields a value for R1 equal to 3.33 x VSW (k). VSW requires an external compensation capacitor to remain stable across the output adjustment range, output capacitance and loading. A value of 220pF between COMPA and COMPB is recommended for all operating conditions with a nominal load capacitance of 1.0F (0.47F to 1.5F). VSW requires a minimum load of 3mA.
FIGURE 6. VSW TRANSIENT RESPONSE, 10mA TO 100mA STEP, VPWR = 18V, AUXIN = 15V, VSW = 12V
Figure 6 depicts the transient response of VSW during a 10mA to 100mA step load when AUXIN is set to 15V and VPWR is set to 18V.
VPWR
VPWR provides the source voltage for the IC and load until AUXIN is back biased. VSW is disabled and the IC operates in a standby (low power consumption) mode when UVLO is active.
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FN6555.1 October 1, 2007
ISL6719
If the application requires high currents or longer start-up times than the thermal protection allows, the device dissipation may be reduced by adding a resistor or resistors in series between the input voltage and VPWR. The dropping resistance must be selected such that VPWR remains above the UVLO threshold of VPWR and at least 6.2V greater than VSW under maximum load and minimum input voltage to maintain regulation.
VIN
ENABLE, ENABLE_N
ENABLE and ENABLE_N are complementary inputs used to turn VSW on and off. Both polarities of the enable function are provided to ease the interface to the application. VSW may be enabled by either ENABLE or ENABLE_N, but both inputs must be logically false to disable the output. Each enable input has a nominal 100k pull-up resistor to 5V.
TABLE 1. ENABLE, ENABLE_N TRUTH TABLE INPUTS ENABLE 0 0 1 ENABLE_N 0 1 0 1 OUTPUT VSW ON OFF ON ON
1 VPWR GND 9 ENABL 8 E_N 2 AUXIN ENABLE 7 3 VSW COMPB 6 COMPA 5 4 VSW_FB
1
FIGURE 7. ADDING DROPPING RESISTORS TO VPWR
The inputs can accept voltages up to 6V maximum down to 0.3V below signal ground. Voltages beyond these limits, including transients, may cause permanent damage to the device. Care should be taken when connecting signal sources through long connections or if significant ground shift could occur between the source and the input. In such circumstances, it is recommended that appropriate clamping networks be used to prevent possible electrical overstress.
Over-Temperature Protection
The ISL6719 has an over-temperature shutdown mechanism to protect the device from excessive dissipation. VSW shutdown occurs approximately at +150C. The hysteresis is large so that the IC has sufficient time to operate at start-up loading levels without re-triggering the over-temperature protection.
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FN6555.1 October 1, 2007
ISL6719 Dual Flat No-Lead Plastic Package (DFN)
2X 0.15 C A A D 2X 0.15 C B
L9.3x3
9 LEAD DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.80 -
NOMINAL 0.90 0.20 REF
MAX 1.00 0.05
NOTES -
A3 b D 0.20
5 INDEX AREA
0.25 3.00 BSC
0.30
4, 7 -
TOP VIEW
B
D2 E
// 0.10 C 0.08 C
1.85
2.00 3.00 BSC
2.10
6, 7 -
E2 e k
0.80
0.95 0.50 BSC
1.05
6, 7 -
A C SEATING PLANE SIDE VIEW A3
0.60 0.25
0.35 9
0.45
7 2 Rev. 0 3/06
L N
D2 (DATUM B) 1 D2/2 2
6
7
NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. All dimensions are in millimeters. Angles are in degrees.
NX k E2
5 INDEX AREA (DATUM A)
4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 6. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 7. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 8. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2.
E2/2
NX L N 7 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 4 SECTION "C-C" CC e TERMINAL TIP (A1) 8L 4 0.10 M C A B
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN6555.1 October 1, 2007

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